The paper 'Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory', written by Song Yong-woon (combined master's–doctoral student) of the Department of Computer Science & Engineering and Professor Lee Hyuk-jun, has been accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. The research proposes a non-volatile memory design that gives network equipment high availability. The packet buffers of existing network equipment use DRAM, a volatile memory, so that when the equipment loses power all buffered content is lost, causing network instability through packet loss. To design a highly available, durable and high-performance packet buffer, the paper proposes 1) a hybrid memory architecture using non-volatile memory in combination, 2) an address mapping method that maximizes memory row buffer locality during packet data processing, and 3) a method for managing the packet data structure (queue). The results showed higher packet throughput and greater energy efficiency than DRAM-based packet buffers.

▲ Professor Lee Hyuk-jun (supervisor), Department of Computer Science & Engineering; Song Yong-woon (combined master's–doctoral student)